XMC-7A50-AP323: XMC module with Artix®-7 FPGA and high density I/O
- Xilinx® Artix®-7 Reconfigurable FPGA
- 48 digital I/O
- 20 Diff analog inputs or 40 SE
- 16-bit ADC
XMC-7A50-AP323 XMC Module with Artix®-7 FPGA and High Density I/O Description
XMC-7A50-AP323: 48 TTL channels Custom requirements: Other I/O combinations are possible, contact Acromag for more information. Build Option A: 24 Channel EIA-485/422 Build Option B: 24 Channel TTL and 12 Channel EIA-485/422 Build Option C: 24 Channel LVDS
Designed for COTS applications, these XMC modules combine a user-customizable FPGA with high-performance digital I/O and analog inputs for high-density signal processing.
The XMC-7A50-AP323 series provides a user-configurable FPGA-based bridge between a host processor and a custom digital interface via PCI Express. These XMC cards feature a best-in-class Artix®-7 interface to deliver the lowest power and highest performance in the industry.
Analog inputs monitor 20 differential channels or 40 single-ended channels. Software or an external hardware input can trigger A/D conversions for synchronization with external events. Built-in precision voltage references enable precise software calibration of the module without external instruments.
The Technical Design Kit provides users with basic information. required to develop custom FPGA firmware to upload to the Xilinx® FPGA. Sample FPGA design code is provided as a Vivado IP Integrator project for features such as one-lane PCI Express interface, DMA, digital I/O control register, etc. Users should be familiar with Xilinx Vivado® design tools.
Key Features and Benefits
FPGA digital I/O
Reconfigurable Xilinx FPGAs
High channel count digital interface: TTL, RS485 and LVDS interface options
32MB quad serial flash memory
52,160 logic cells
65,200 flip flops
2700 KB block RAM
120 DSP slices
External LVTTL clock input
Long distance data transmission
System power on and reset are fail safe
20 differential inputs or 40 single-ended inputs
· Flexible scanning control
16-bit A/D resolution
8μs conversion time
FIFO buffer with 16K sample memory
Interrupt on FIFIO threshold condition
FIFO full, empty and threshold reached flags
Programmable channel conversion control
· Programmable conversion timer
Multiple scanning modes
Wide temperature range
Conduction cooling options
Software development tools for VxWorks®, Linux® and Windows® environments
Complies with ANSI/VITA 42.0 specification for XMC module mechanical components and connectors.
Compliant with ANSI/VITA 42.3 specification for XMC modules with PCI Express interface.
Electrical/mechanical interface: single-width module.
PCI Express Base Specification
Complies with revision 2.0
Lanes: 1 lane in each direction.
Bus speed: 2.5 Gbps (Generation 1).
Memory: 128k space required. 1 base address register.
FPGA device: Xilinx Artix-7 FPGA model XC7A50T.
FPGA configuration: download via flash memory.
Sample FPGA program: Provided IP integrator block diagram for PCIe bus 1 lane Gen 1 interface, DMA controller, on-chip RAM, flash memory, and field I/O control. See EDK kit.
Field I/O Interface: PCIe 1 lane bus Gen 1 interface.
I/O connector: 100-pin field I/O connector.
Technical design kit
Provides the user with the basic information needed to develop a custom FPGA program. The kit must be ordered with the first purchase of an XMC-7A50-AP323 series module
(see www.acromag.com for more information).
48 input/output channels. Direction is controlled in groups of eight channels. 5V tolerant.
TTL electrical characteristics
HIV: 2.0 V minimum.
VIL: 0.8V maximum.
VOH: 2.0V minimum.
VOL: 0.55V maximum at 64mA.
Input configuration: 20 differential or 40 single-ended.
A/D resolution: 16 bit.
Input range (DIP switch selectable)
Bipolar ±5V or ±10V.
Unipolar 0 to +5V or 0 to +10V.
Data sample memory: 16 KB sample FIFO buffer.
Maximum rate: 200KHz (5μS/conversion).
A/D triggers: External and software.
System accuracy: 2.4 LSB (0.014%).
Maximum global calibrated error at 25°C.
Data format: Binary two’s complement and pure binary.
Input overvoltage protection: Power up: -20V to +40V. Off: -35 V to +55 V
Common mode rejection ratio (60 Hz): 96 dB typical.
Channel-to-channel rejection rate (60 Hz): 96 dB typical.
Operating temperature: -40 to 70°C.
Storage temperature: -55 to 100°C.
Relative humidity: 5 to 95% non-condensing.
Length: 5.866 inches (143.75 mm.)
Width: 2.9134 inches (74 mm.)
Weight: 3.392oz (96.162g).